This relates to integrated circuits, and more particularly, to integrated circuits with guard rings.
Integrated circuits typically include digital circuitry, analog circuitry, and/or other functional circuitry formed in a semiconductor substrate. In a typical scenario, the internal circuitry within an integrated circuit is coupled to external equipment through input-output pads. Noise can potentially leak from the external equipment through the pads onto the internal circuitry. Noise entering an integrated circuit via the input-output pads or noise from one active/aggressor circuit to another victim circuit within the integrated circuit can degrade circuit performance, particularly in high-speed applications.
In an effort to provide better noise isolation, integrated circuits are often provided with guard rings. For example, a guard ring may be formed around the internal circuitry to help block noise leaking into the integrated circuit from the external equipment. As another example, a guard ring may be formed around a sensitive circuit to isolate that sensitive circuit from noise or interference generated from nearby circuitries on the integrated circuit.
Conventional guard rings that are formed on integrated circuits with planar complementary metal-oxide-semiconductor (CMOS) transistors (i.e., transistors having polysilicon gate conductors formed over a planar substrate on a gate oxide liner) are formed by implanting dopants into the planar substrate to construct diffusion regions in wells of the same doping type. For example, a p+ diffusion region is formed in a p-well to form a p+ guard ring, whereas an n+ diffusion region is formed in an n-well to form an n+ guard ring. High density Ohmic contacts are formed directly on the n+/p+ diffusion regions to help bias the diffusion region to appropriate voltage levels. Conventional guard rings formed in this way can be formed as a solid continuous (i.e., non-broken) ring structure around a particular circuit that is being isolated.
To provide improved control of transistor devices at smaller technology nodes, multi-gate “non-planar” transistor structures such as Fin field-effect transistors (FinFETs) have been developed. Fabrication design rules for FinFETs, however, limit the width of the diffusion regions. As a result, a guard ring formed on an integrated circuit with FinFET devices cannot be formed as a solid continuous ring structure and will therefore exhibit gaps along the periphery of the guard ring. Noise propagating through these gaps can severely limit circuit performance, especially when the substrate exhibits low resistance, which is typical for the FinFET processing technology.
It is within this context that the embodiments herein arise.